Delta Developments

Boxcar Detectors

(Boxcar Integrator, Gated Integrator, Gated Averager)

Boxcar Detectors are also called Boxcar Integrators, Gated Integrators, Boxcar Averagers and Chopped Signal Integrators. Their main purpose is to process the signals obtained from a chopped light beam detected by pyro-electric, photoconductive, photovoltaic or photomultiplier detectors. However, they can also be used on any signal which has a constant phase relationship to a synchronizing pulse.

The system provides a steady output from the pulsed signals by averaging the input during the periods of signal ‘on’ and subtracting this from the input averaged during periods of signal ‘off’.

The different response times of different detectors are accommodated by varying the duration and timing of the time windows accepting ‘on’ values or ‘off’ values. This provides a degree of flexibility not normally available even in a costly Phase Sensitive Detector.

We make two types of system using either one or two stages.

Simple Chopped Signal Integrator

Simple Signal Integrator

Operation. The synchronising signal from the chopper is delayed and stretched to define two time windows: one for the moments of signal and the other for the moments of zero. The voltages during these two time windows are integrated separately and the integrals then subtracted to give a steady output signal. The DVM thus displays the peak to peak height of the original chopped signal but with the fluctuation due to noise much reduced. Initially, an oscilloscope is needed to set the two time windows to positions suited to the detector response time. An LED warns if the windows are overlapping. Once set correctly, the ’scope is not then needed because the windows are very stable in both timing and duration.

For this Simple System the standard delays give a range of chopping frequencies from 20 - 400Hz. and a full scale deflection of 10mV to 10V.   The ranges of the delay time, window time and allowed input voltages can all be varied on request.

An output pulse is provided to allow synchronisation of the chopper to the supply frequency so that variable 50/60Hz pick-up can be reduced.

Time and Freq. Limits Frequency Range 20 - 400Hz (standard)
Delay Time Range 100µs - 8ms (set by 10 turn preset on front panel)
Aperture Time Range 15µs - 1ms (set by 10 turn preset on front panel)
Signal Inputs Input Ranges 0.1V, 1.0V, 10V (standard)
Input Impedance 1.0M Ohm, 20pF
Independent Amplifier Gain x10 (within ±1%)
Rise-Time 70µs (10-90%) = 5kHz
Input Impedance 1.0M Ohm, 20pF
Output Impedance 10k Ohm
Signal Outputs Settling Time Typically 0.4 secs to 2%
Display 3.5 digit DVM integral with Unit
Output Signal 0 - 10V from 1.0k Ohm impedance
Window pulses 5V TTL. These outputs show the active periods of signals and zeroes integrators
Overall Accuracy 1.5% abs. accuracy of conversion from chopped signal to DC
Synchronisation I/P sync. pulse required 3.5 - 10V into 10k Ohm for >3µs at 20 - 400Hz
O/P locked to supply 5V from 500 Ohms for 0.7ms at 50/60Hz
Can drive ‘Sync In’ Socket on Chopper
Optional Count-down Module Allows synchronisation at a lower frequency of your choice.  e.g. every 10th mains cycle to give 5Hz
Noise Reduction and Common Mode Range

Although noise reduction is not the prime object of this Unit, it will nevertheless normally give substantial reductions in any noise asynchronous to the chopping frequency as below (using the definition of dB used in electronics whereby 20dB = x10 in voltage):

Noise Frequency (Hz) 30 100 300 1000
Noise Reduction (dB) 30 50 70 90

Noise at exactly the signal frequency (for example 50Hz pick-up with a 50Hz chopper) obviously must appear as an unwanted offset in the output. This offset can be backed off with the ten turn potentiometer on the front panel. The stability of this back-off voltage is 0.1% of Full Scale Reading. Up to 2x Full Scale Reading can be backed off.

For Noise at a multiple of the signal frequency, a reduction of 50dB is typical depending on the exact situation.

Power Consumption 5W at 240/115V AC 50/60Hz
Weight 4.5kg
Dimensions 25cm wide, 15cm high, 29cm deep

Advanced Signal Integrator

To understand the need for an Advanced Signal Integrator we should consider first the operation of a simple system. This will probably have two main features:

  1. If the signal is known to occur within an exactly known interval after a trigger pulse, the system can acquire the signal during that time and ignore all the noise or false signals before and after the acquisition window. The output is a steady DC signal equal to the signal value during the time window. There may be a similar channel for moments when the signal is known not to be there (acquisition of Zero value); in this case the final result is then the difference in the two outputs.
  2. It can provide smoothing of the signal from one sampling window to the next by integrating the signal over many cycles. However, this requires storage of the signal from one cycle to the next in a circuit like the one below.
Leaky Integrating Switch

The switch might be a FET with a leakage resistance of Rleak when OFF.  Rsource includes the output impedance of the preceding amplifier and the resistance of the switch when ON.  Rstore includes the input impedance of the following amplifier.

If the switch is closed for a time D when the signal is present then to get total acquisition of the signal in just one pulse we need [Rsource]*[Cstore] to be substantially less than D. If the time between pulses is t (t = the cycle time) then to preserve the signal from one acquisition to the next we require that [Rleak]*[Cstore] be very much greater than t.

Now consider the limitations when D is very small but t is very long. Typically, Rsource can hardly ever be less than 100 Ohms so that if D =100ns, Cstore can only be 200pF to allow a full charge up at each cycle. Now, with the switch open the stored charge decays through Rleak and Rstore in parallel.  These two in parallel are rarely more than 10MΩ so that, once the switch is open, the signal decays with a 1/e time constant of about 2ms.  If a 1% decay between cycles is acceptable then the maximum cycle time must not exceed 1% of the decay time. This gives a required cycle time of <20microseconds or a required PRF of >50kHz).

Thus, for very low duty cycle signals when we want accumulation from one cycle to the next, the acquisition must be done by a more complex method in which the signal on the capacitor Cstore is captured before it can decay. There are two possible schemes:

Our Advanced Integrator System uses Scheme 2. The signal stored on the capacitor is captured on a fast A/D Converter before it can decay. The digital storage has a partial update system so that at each cycle the digital value stored may be only slightly changed by the new value. For example at each cycle we might take 1/8 of the new value and add it to 7/8 of the old value which had been stored before the new data arrived. Thus at any given time we are storing the accumulation of all the previous data. This system provides essentially exponential smoothing and gives a corresponding reduction in both noise and in any fluctuations in the actual signal.

A switch on the front panel controls the number of points for the exponential smoothing which can be 1, 2, 4... up to 128. For a setting of ‘0’ the data is totally updated in one shot and there is no smoothing effect; this setting would normally be used for single shot operation.

Typical Specification for Advanced System
Signal Window Aperture Adjustable from 10ns to 3ms (other values may be possible)
Zeroes Window Aperture Also 10ns to 3ms
Window Aperture controls Front Panel Potentiometers give separate control of signal window duration and zero window duration.
Signal Window Delay Adjustable from 30ns to 100ms (other values possible)
Zeroes Window Delay Also 30ns to 100ms
Window Delay controls Front Panel Potentiometers give separate control of signal window delay and zeroes window delay.
Processing Cycle Time The digital processor needs 10µs to complete its processing. This therefore limits the repetion rate to 100kHz.
Full scale range Range switch selects 1mV, 10mV, 100mV, 1V
Allowed over range Typically the ratio of P-P Noise to Signal can be at least 10:1
Smoothing/Accumulation Digital accumulation over 1 or 2 or 4 etc up to 128 samples
Reduction in Random Noise Typically x20 but depends on detail of source of noise.
Reduction in Fluctuation of Signal Typically x20 - x200 but depends on detail of fluctuations
  A Technical Note discussing random noise, signal fluctuation and the possible reduction in fluctuations is available on request.
Display DVM with 3.5 Digits
Output 1V FSD from 100 Ohm impedance BNC Socket.
Trigger input required 1-3V into BNC Socket (input impedance 1k Ohm). All timings are w.r.t. rising edge of trigger I/P