Delta Developments

Chopped Signal Integrator
or Phase Sensitive Detector
or Boxcar Detector

• Ideal for Pyroelectrics, Photomultipliers, Si, CMT Detectors
• Subtracts averaged ‘off ’ time values from averaged ‘on’ time values
• Sync output locks chopper to Line frequency to eliminate variable pick up
• 1M Ohm input impedances
• Independent on board x100 Amplifier
• Simple Systems down to 100µs aperture time.
• Advanced Systems down to 30ns aperture time.

The Boxcar Detectors (also called Chopped Signal Integrators or Phase Sensitive Detectors) are designed to process the signals obtained from a chopped light beam detected by a pyroelectric, photoconductive, photovoltaic detector or a photomultiplier. However, they can also be used on any signal which has a constant phase relationship to a synchronizing pulse.

The system provides Synchronous Detection (or Boxcar Integration) to give a steady output even from low level signals by averaging the input during periods of signal ‘on’ and subtracting this from the averaged input during periods of signal ‘off’.

The different response times of different detectors are accommodated by varying the duration and timing of the time windows accepting ‘on’ values or ‘off’ values. This provides a degree of flexibility not normally available even in a costly lock-in system.

We make two broad types of system – using either one or two stages.

• The Simple System achieves its integration of the signal in one stage of capacitor storage.
• The Advanced System has first a stage of analogue storage on a capacitor and then digital storage of that result. This allows for very short window times at low repetition rates.

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Simple Signal Integrator

Operation. The synchronising signal from the chopper is delayed and stretched to define two time windows: one for the moments of signal and the other for the moments of zero. The voltages during these two time windows are separately integrated and then subtracted to give a steady output signal. The DVM thus displays the peak to peak height of the original chopped signal but with the fluctuation due to noise much reduced. An Oscilloscope would normally be used to set the time windows to positions best suited to the different detector response times. Once set correctly, the ’scope is not needed because the windows are very stable in both timing and duration. An LED warns if the windows overlap in time.

The chopping frequency range of this simple system is 20 - 400Hz. Full scale deflection of 100µV to 10V can be covered in the presence of twice as much noise or common-mode signal. A pulse is provided to synchronise the chopper to the supply frequency so that variable 50/60Hz pick-up can be reduced.

Time and Freq.Limits	Frequency Range	20 - 400Hz
	Delay Time Range	0.1 - 25ms (set by 10 turn preset on front panel)
	Aperture Time Range	0.1 - 25ms (set by 10 turn preset on front panel)
Signal Inputs	Input Ranges	0.1V, 1.0V, 10V
	Input Impedance	1.0M Ohm, 20pF
Independent Amplifier	Gain	x100 (within ±2%)
	Rise-Time	70µs (10-90%) = 5kHz
	Input Impedance	1.0M Ohm, 20pF
	Output Impedance	10k Ohm
Signal Outputs	Settling Time	Typically 0.4 secs to 2%
	Display	3.5 digit DVM integral with Unit
	Output Signal	0 - 10V from 1.0k impedance
	Window pulses	5V TTL. Show active periods of signals and zeroes integrators
	Overall Accuracy	2% abs. accuracy of conversion from chopped signal to DC
Synchronisation	I/P sync. pulse required	3 - 10V into 10k Ohm for >2µs at 20 - 400Hz
	O/P locked to supply	5V TTL for 1ms at 50/60Hz Can drive ‘Sync In’ Socket on Chopper

Noise Reduction and Common Mode Range

Although noise reduction is not the prime object of this Unit, it will nevertheless normally give substantial reductions in any noise asynchronous to the chopping frequency as below (using the definition of dB used in electronics whereby 20dB = x10 in voltage):

Noise Frequency (Hz)	30	100	300	1000
Noise Reduction (dB)	30	50	70	90

Noise at exactly the signal frequency (for example 50Hz pick-up with a 50Hz chopper) obviously must appear as an unwanted offset in the output. This offset can be backed off with a ten turn preset on the front panel. The stability of the back-off voltage is 0.1% of Full scale Reading. Up to 2x Full Scale Reading can be backed off.

For Noise at a multiple of the signal frequency, a reduction of 50dB is typical depending on the exact situation.

Power Consumption	2W at 240/115V AC 50/60Hz
Weight	1.5kg
Dimensions	23.5cm wide, 9cm high, 17cm deep

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Advanced Signal Integrator

To understand the need for an Advanced Signal Integrator we should consider first the operation of a simple system. This will probably have two main features:

1. If the signal is known to occur within an exactly known interval after a trigger pulse, the system can acquire the signal during that time and ignore all the noise or false signals before and after the acquisition window. The output is a steady DC signal equal to the signal value during the time window. There may be a similar channel for moments when the signal is known not to be there (acquisition of Zero value); in this case the final result is then the difference in the two outputs.
2. It can provide smoothing of the signal from one sampling window to the next by integrating the signal over many cycles. However, this requires storage of the signal from one cycle to the next in a circuit like the one below.

The switch might be a FET with a leakage resistance of [R_leak] when OFF. [R_source] includes the output impedance of the preceding amplifier and the resistance of the switch when ON. [R store] includes the input impedance of the following amplifier.

If the switch is closed for a time D when the signal is present then to get total acquisition of the signal in just one pulse we need [R_source]*[C_store] to be substantially less than D. If the time between pulses is t (t = the cycle time) then to preserve the signal from one acquisition to the next we require that [R_source]*[C_store] be very much greater than t.

Now consider the limitations when D is very small but t is very long. Typically, [R_source] can hardly be less than 100 Ohms so that for D =100ns, [C store] can only be 200pF to allow a full charge up at each cycle. Now, with the switch open the stored charge decays through both [R_leak] and [R_store]. These two in parallel are rarely more than 10MΩ so that, once the switch is open, the signal decays with a 1/e time constant of about 2ms. If a 1% decay between cycles is acceptable then the maximum cycle time must not exceed 1% of the decay time. This gives a required cycle time of <20microseconds or a required PRF of <50kHz).

Thus, for very low duty cycle signals when we want accumulation from one cycle to the next, the acquisition must be done by a more complex method in which the signal on the capacitor C_store is captured before it can decay. There are two possible schemes:

• Scheme 1. This uses two analogue stages (one fast and one slower)
• Scheme 2. This uses one analogue stage followed by digital storage of the result.

Our Advanced Integrator System uses Scheme 2. The signal stored on the capacitor is captured on a fast A/D Converter before it can decay. The digital storage has a partial update system so that at each cycle the digital value stored may be only slightly changed by the new value. For example at each cycle we might take 1/8 of the new value and add it to 7/8 of the old value which had been stored before the new data arrived. Thus at any given time we are storing the accumulation of all the previous data. This effectively provides essentially exponential smoothing and gives a corresponding reduction in noise. Of course, this system also reduces fluctuations that may be present in the actual signal.

A switch on the front panel controls the number of points for the exponential smoothing which can be 1, 2, 4... up to 256. For a setting of ‘0’ the data is totally updated in one shot and there is no smoothing effect; this setting can be used for single shot operation.

Typical Specification

Signal Window Aperture	Adjustable from 30ns to 3ms (other values may be possible)
Zeroes Window Aperture	Also 30ns to 3ms
Window Aperture controls	Front Panel Potentiometers or 0-1V into BNC sockets. There is separate control of signal window duration and zero window duration.
Signal Window Delay	Adjustable from 30ns to 100ms (other values possible)
Zeroes Window Delay	Also 30ns to 100ms
Window Delay controls	Front Panel Potentiometers or 0-1V into BNC sockets. There is separate control of signal window delay and zero window delay.
Processing Cycle Time	The digital processor needs 10µs to complete its processing. This therefore limits the repetion rate to 100kHz.
Full scale range	Range switch selects 1mV, 10mV, 100mV, 1V
Allowed over range	Typically the ratio of P-P Noise to Signal can be at least 10:1
Smoothing/Accumulation	Digital accumulation over 1 or 2 or 4 etc up to 256 samples
Reduction in Random Noise	Typically x20 but depends on detail of source of noise.
Reduction in Fluctuation of Signal	Typically x20 - x200 but depends on detail of fluctuations
	A Technical Note discussing random noise, signal fluctuation and the possible reduction in fluctuations is available on request.
Display	DVM with 3.5 Digits
Output	1V FSD from 100 Ohm impedance BNC Socket.
Trigger input required	1-3V into BNC Socket (input impedance 1k Ohm). All timings are w.r.t. rising edge of trigger I/P